1. Field of the Invention
The present invention is directed to the manufacture of masks used in the lithographic production of integrated circuits and, in particular, to the inspection and detection of metallized defects on patterned masks.
2. Description of Related Art
The manufacture of semiconductor substrates such as wafers and chips involve the use of high-resolution lithography systems. In such systems, a patterned mask (i.e., reticle) is illuminated with radiation (e.g., laser radiation or radiation from an arc lamp) that passes through the illumination system and achieves a high-degree of illumination uniformity over the illuminated portion of the mask.
FIG. 1 shows a typical prior art mask 80 with a device exposure region 82 having a square or rectangular shape positioned at the center of the mask and an opaque region 84. The device exposure region includes transparent portions that may be made of glass, quartz, or the like, and opaque portions commonly made of chrome for defining a device pattern 88 (which is not illustrated in detail in the figure). As an alternative, phase shifting masks (PSMs) have also been employed in order to increase the resolution of the critical active area patterns projected on the mask. The increased resolution of PSMs enables smaller line widths and tighter pitches to be exposed on the resist and consequently etched into or deposited on the wafer substrate.
Also within the mask is a kerf region 86, or discardable portion of the semiconductor wafer, that resides at the periphery of the device region 82 and contains important information regarding the photolithographic process of the wafer and usually includes test structures to verify the performance of the photolithographic process. Illumination from a light source is allowed to travel through the transparent portions in the device exposure region, while the opaque regions block the light such that light does not reach the wafer.
Since an ongoing concern in semiconductor technology is the maximization of manufacturing yield, it has become conventional to fabricate intentionally induced defect test structures (i.e., 2P (“phase shift”) level shapes) isolated from the production circuits that serve to yield reliability data on the regular product circuits. The principal reason for fabricating these defect test structures is that the integrated circuits themselves cannot be probed because the interconnections in the device are neither accessible electrically nor can the regions be isolated from one another to provide accurate data.
The intentionally induced defect structures are commonly formed in the kerf region of the mask and comprise metallized structures, typically made of chrome. As such, when imaging the wafer using the mask, the defect structures and the imaging pattern are transferred to the same wafers on which the actual semiconductor devices are fabricated. In so doing, the defect test structures are fabricated in exactly the same processing environment at exactly the same time as the actual semiconductor devices. This allows the intentionally induced defect structures to be more accurately indicative of the processing defects that will occur in the actual products.
However, during the process of inspecting the masks for defects, the intentionally induced defect structures may introduce a significant amount of false and nuisance noise. This is particularly true for those masks having reduced dimensions that must be inspected at reduced sensitivities.
Conventional approaches aimed at avoiding detection of intentionally induced defect test structures have been to reduce the sensitivity at which the inspection tool is run. However, it has been found that by running inspection tools at reduced sensitivities, processing-induced defects residing on the mask may not be detected by the inspection tool, especially for masks with reduced sizes. If not detected, these defects can ultimately lead to product failure. Another approach has been to manually inspect the mask for intentionally induced defects, and to designate any located intentionally induced defects as do not inspect regions (i.e., those regions of the mask that the inspection tool will not inspect). Yet this approach is undesirably tedious, time consuming and often prone to mistakes, either by missing some intentionally induced defects and/or by misplacement of the do not inspect regions.
As such, due to current semiconductor devices having reduced dimensions, and with future generations that will have even smaller dimensions, a need exists in the art for providing improved methods, systems, articles and program products for the detection of metal defects on patterned masks.